1. Field of the Invention
The invention relates generally to a method of programming/reading a multi-level flash memory using a sensing circuit. More particularly, the invention is concerned with a method of programming/reading a multi-level flash memory using a sensing circuit capable of simply processing a plurality of bit information of each of the cells that are sequentially processed and allowing a low current operation, by maximizing the number of a sense amplifier to increase the number of cells that could be processed at a time.
2. Description of the Prior Art
A general method of programming a flash memory includes an iterative program verification technique in which a desired threshold voltage is obtained by repeatedly performing program and verification.
A method of reading a conventional multi-level flash memory is process the sense amplifier having the number of comparators below one than the number of the threshold voltage level of the flash memory cell to process a plurality of bit data at a time or to process plural bit data by allowing a multiple sensing operation by a single comparator while changing the reference voltage.
FIG. 1 is a circuit diagram shown to explain a method of programming/reading a multi-level flash memory using a conventional sensing circuit according to a first embodiment, which shows a circuit for sensing 4 (four) levels.
As shown in FIG. 1, the sensing circuit for programming/reading the multi-level flash memory includes a PMOS transistor PM1 a source of which is applied a power supply voltage VDD and drain and gate of which are commonly connected, wherein the commonly connected drain and gate is connected to a drain of a selected cell; a reference voltage generator 5 for generating first˜third reference voltages VREF1˜VREF3 first˜third comparators 1˜3 a first input terminal of which is connected to the drain of the selected cell FMC and second input terminals of which are applied first˜third reference voltages VREF1˜VREF3 respectively, for outputting the compared results X1˜X3 and a decoder 4 for decoding outputs X1˜X3 of the first˜third comparators 1˜3 to output 2 bit data MSB, LSB.
An operation of the sensing circuit for programming/reading the conventional multi-level flash memory constructed as above will be described as follows.
If a drain current is generated by applying a given voltage VG to the control gate of the multi-level flash memory cell FMC having four threshold voltage distributions, first˜third comparators 1˜3 change the drain current value correspondingly generated to the threshold voltage of the cell FMC into voltages in order to compare them with three reference voltages VREF1˜VREF3 simultaneously. Then, the comparison results X1˜X3 are decoded by the decoder 4 to represent information on at which step of the four levels the threshold voltage of the cell FMC is located using 2 (two) bit data MSB, LSB.
FIG. 2 is another circuit diagram shown to explain a method of programming/reading a multi-level flash memory using a conventional sensing circuit according to a second embodiment, which shows a circuit for sensing four levels.
As shown in FIG. 2, the sensing circuit for programming/reading the multi-level flash memory includes a PMOS transistor PM11 a source of which is applied a power supply voltage VDD and drain and gate of which are commonly connected, wherein the commonly connected drain and gate is connected to a drain of a selected cell; a reference voltage generator 13 for generating a reference voltage VREF a comparator 11 one terminal of which is connected to the drain of the selected cell FMC and the other terminal of which is connector to the reference voltage VREF and a decoder 12 for decoding the output of the comparator 11 to produce 2 bit data MSB, LSB.
An operation of the sensing circuit for programming/reading the conventional multi-level flash memory constructed as above will be described as follows.
Three types of voltages corresponding to a middle voltage value of each of four threshold voltages are sequentially applied to a control gate of the flash memory cell over three steps with them being increased or decreased. The comparator 11 senses whether a drain current flows in the cell FMC in every step to sense the control gate voltage in the step where the drain current starts to flow or the step where the current does not flow. Then, the decoder 12 receives the output of the comparator 11 to represent information on at which step of the four threshold voltage levels the threshold voltage of the cell FMC is located using 2 (two) bit data MSB, LSB.
As can be seen from the above, the conventional method of programming/reading the multi-level flash memory using the sensing circuit according to the first embodiment has disadvantages that it requires additional program circuit and its execution procedures are complicated. In addition, the method of reading the multi-level flash memory is simple in the operation of the circuit. However, there is a disadvantage that its sensing circuit becomes greater. Further, the conventional method of programming/reading the multi-level flash memory using the sensing circuit according to the second embodiment is simple and can be easily applied to a unit cell. However, there is a disadvantage that the method is difficult to be implemented within an actual memory array. In addition, there is an advantage that it requires circuits for program and read, respectively.